Currently almost 100% of all electronic components are tested prior to assembly onto circuit boards. Such testing is highly desirable as in circuit board assembly processes up to 80,000 components may be used in each assembly line per minute. If a single component is defective, it is typically more cost effective to scrap the entire finished circuit board, rather than identify and repair any manufacturing defects.
As the speed of electronic circuitry manufacture has increased, various manufacturers have developed automatic test equipment to test and validate individual components. Conventional automatic test equipment typically includes a master controller which is electronically coupled to a signal simulator, sensing card or the like by way of a connector interface and mass interconnect system. The mass interconnect system is provided with a mounting table used to position and electronically couple a component device or unit under test to the simulator during testing. A robot handler physically positions the component device or unit under test to be tested within the automatic test equipment. Conventional automatic test equipment used to test individual components however, currently experience difficulties keeping pace with faster assembly speeds. In particular, conventional automatic test equipment (ATE) is limited to less than 12 GHz, and most typically operates at about 4 GHz.
Various manufactures have proposed automatic test systems which operate to test components at speeds as high as 77 GHz. However, major constraints exist with adopting higher processing speeds, as a result of limitations on current mass interconnect system mounting tables. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. In particular, signal integrity degradation due to parasitic effects of interconnects and electromagnetic coupling undermines the test results at high speeds.
Conventional automatic test equipment incorporate a device interface unit to perform tests on integrated circuits. The device interface unit provides temporary electrical connections between the component or unit under test and the measurement instruments within the ATE. The device interface unit also provides space for unit under test-specific local circuits, such as buffer amplifiers and load circuits. The applicant has appreciated that it is highly desirable to reduce the physical distance between the unit under test and the testing circuitry of the ATE to lower transmission line effects and the electromagnetic coupling. One traditional approach is to locate the mounting table pin electronics of the automatic test equipment as close as possible to the unit under test pins. However, in practice general purpose pin electronics are designed to meet a variety of requirements to cover different test scenarios. As a result, general purpose pin electronics are commonly bulky and cannot be readily integrated and positioned adjacent to the unit under test pins. Furthermore, conventional mounting tables consume considerable amounts of power, and in some cases require liquid cooling systems to avoid overheating and maintain desired temperature. Heretofore, the problem of physical separation between unit under test and pin electronics has not been decisively solved. As a result, heretofore in the state of the art automated test equipment (ATE), this distance still may exceed several inches.
To reduce the length of transmission distance between the automated test equipment and unit under test, various techniques have been considered. In certain applications, test head circuitry may be removed from the mass interconnect assembly and located remotely in an attached mainframe chassis. In such constructions, comparators, programmable loads, drivers and switching circuits are typically left in the test head. The circuits are then integrated on a low power monolithic circuit to facilitate packaging and reduce cooling requirements. Although designing a pin electronics board in such a manner reduces the total length between the unit under test outputs and comparators inputs to approximately 2 to 3 inches for a conventionally packaged VLSI device, a 2 to 3 inch gap may still undermine signal integrity when frequencies exceed a few gigahertz.
Alternately, general purpose pin electronics may be replaced with device specific receivers. By restricting the pin electronics architecture to only a single device, the power and area overhead are reduced. Transceivers may then be fabricated and mounted on the unit under test interface board to serve as a local test interface. While such changes allow the characteristics of the inputs and outputs of the test system to be matched to the component or unit under test I/O pad and reduce both the effects of signal reflection as well as the distance between the device under test and pin electronics, such approach restricts the flexibility of the general purpose pin electronics architecture.
The applicant has appreciated that with the transient frequency of available complimentary-symmetry metal-oxide-semiconductor (CMOS) technologies exceeding 200 GHz, the architecture of the conventional testers needs to be greatly improved to maintain acceptable testing speeds. High-speed test signals experience a broad range of nonlinearities associated with the signal paths. It has been recognized that when the frequency of interaction between the unit under test and the automatic test equipment approaches the gigahertz range, the effects of transmission lines become a critical issue requiring matching impedances to minimize signal reflection and enhance the performance parameters of test channels. Moreover, AC resistance due to the skin effect and electromagnetic coupling caused by radiation become significant, degrading the signal integrity. These undesired effects eventually undermine the timing measurement accuracy and the test results.